The invention relates generally to adders, and more particularly, to circuits and methods for selectively latching the output of an adder.
A microprocessor typically includes an arithmetic unit. The arithmetic unit typically includes an adder. A portion 10 of such an adder is shown in FIG. 1.
The illustrated portion 10 of the adder includes first and second exclusive or (XOR) gates 12, 14. One of the XOR gates 12, 14 develops an answer with a carry 1 signal. The other of the XOR gates 12, 14 develops an answer with no carry 1 signal.
The output signals of the XOR gates 12, 14 are respectively inverted by a pair of inverters 16, 18. The outputs of the inverters are coupled to a conventional sum select multiplexer 20.
The multiplexer 20 is responsive to a select signal to output one of the input signals received from the first inverter 16 and the input signal received from the second inverter 18. The output of the multiplexer 20 is inverted by an inverter 22. The output of the inverter 22 is latched by a latch 24.